The primary effort involved designing a MIPS processor architecture using a Hardware Description Language (HDL, e.g., VHDL or Verilog) and synthesizing it onto an FPGA. This logical design defined the processor's datapath, control unit, registers, and instruction set execution. Electrical interfacing involved connecting the FPGA's UART pins for communication. The software component included developing a custom compiler and assembler toolchain capable of converting code written in a higher-level language or assembly into machine code executable by the bespoke MIPS core implemented on the FPGA. A communication protocol over UART was implemented on the FPGA to receive this compiled code.